Veryl is a modern hardware description language designed as a SystemVerilog alternative, providing optimized syntax, interoperability, and productivity tools for efficient hardware design.
Features
Real-time diagnostics
Notifies issues such as undefined, unused, or unassigned variables in real-time while editing, helping to catch errors early and improving code quality.
Auto formatting
Provides automatic code formatting integrated with the editor and command line, ensuring consistent style and reducing formatting-related edits.
Integrated test
Allows embedding SystemVerilog or cocotb test code directly in Veryl and executing tests via the `veryl test` command for seamless testing.
Dependency management
Built-in feature for managing library dependencies by specifying repository paths and versions, simplifying project configuration.
Generics
Supports generics for modules and functions, enabling more reusable code without traditional parameter overrides.
Clock Domain Annotation
Ensures safe clock domain crossing by requiring explicit clock domain annotations, reducing errors and improving design reliability.
Trails comma
Facilitates code maintenance by allowing trailling commas in lists, making it easier to add and remove elements.
Abstraction of clock and reset
Provides syntactical abstraction for clock and reset signals, allowing configuration flexibility for different hardware targets.
Documentation comment
Supports Markdown and other formats for writing module documentation, allowing auto-generation of documentation.
Compound assignment operator
In `always_ff` blocks, non-blocking assignments are inferred, allowing the use of compound assignment operators similar to `always_comb`.
Individual namespace of enum variant
Prevents name collisions by defining enum variants within separate namespaces for each enum.
`repeat` of concatenation
Improves readability in bit concatenation by using `repeat` syntax for repetition descriptions.
`if` / `case` expression
Improves code readability by replacing ternary operators with `if` and `case` expressions.
Range-based `for` / `inside` / `outside`
Simplifies range expressions using closed and half-open interval notations for `for`, `inside`, and `outside` constructs.
`msb` notation
Eliminates the need for manually calculating the most significant bit from parameters, clarifying intentions in code.
`let` statement
Provides a `let` statement for value binding simultaneously with variable declaration, adding flexibility to code structure.
Named block
Allows defining named blocks to limit variable scope, organizing code in a more readable and manageable way.
Visibility control
Uses `pub` keyword to control module visibility, distinguishing between external and internal project elements.